/*****************************************************************************
 * hal_hi_gpio.c
 *
 * Copyright (C) 2019 Jeasonvor <1101627719@qq.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 *
 ****************************************************************************/

/*****************************************************************************
 * Included Files
 ****************************************************************************/

#include "plum_api.h"
#include "hal/source/hal_hi/hal_hi.h"

/*****************************************************************************
 * Trace Definitions
 ****************************************************************************/
#define LOG_RUN_LEVEL LOG_LEVEL_DEBUG
#define LOG_MODULE    "hal.gpio"
#include "thirdparty/log/log.h"
/*****************************************************************************
 * Pre-processor Definitions
 ****************************************************************************/

#define HAL_HI_GPIO_FUNC(id) HI_IO_FUNC_GPIO_##id##_GPIO

/*****************************************************************************
 * Private Types
 ****************************************************************************/

typedef struct {
    plum_u32 id;
    plum_void (*func)(plum_u32 id);
    struct list_head list;
} hi_gpio_irq_t;

/*****************************************************************************
 * Private Function Prototypes
 ****************************************************************************/

/*****************************************************************************
 * Private Data
 ****************************************************************************/

PLUM_PRIVATE hi_gpio_irq_t gpio_irq_head;

/*****************************************************************************
 * Public Data
 ****************************************************************************/

/*****************************************************************************
 * Private Functions
 ****************************************************************************/

PLUM_PRIVATE
hi_io_name hal_hi_gpio_name(plum_u32 id)
{
    hi_io_name name = HI_IO_NAME_MAX;

    switch (PLUM_HAL_GPIO_PIN(id)) {
        case 0:
            name = HI_IO_NAME_GPIO_0;
            break;
        case 1:
            name = HI_IO_NAME_GPIO_1;
            break;
        case 2:
            name = HI_IO_NAME_GPIO_2;
            break;
        case 3:
            name = HI_IO_NAME_GPIO_3;
            break;
        case 4:
            name = HI_IO_NAME_GPIO_4;
            break;
        case 5:
            name = HI_IO_NAME_GPIO_5;
            break;
        case 6:
            name = HI_IO_NAME_GPIO_6;
            break;
        case 7:
            name = HI_IO_NAME_GPIO_7;
            break;
        case 8:
            name = HI_IO_NAME_GPIO_8;
            break;
        case 9:
            name = HI_IO_NAME_GPIO_9;
            break;
        case 10:
            name = HI_IO_NAME_GPIO_10;
            break;
        case 11:
            name = HI_IO_NAME_GPIO_11;
            break;
        case 12:
            name = HI_IO_NAME_GPIO_12;
            break;
        case 13:
            name = HI_IO_NAME_GPIO_13;
            break;
        case 14:
            name = HI_IO_NAME_GPIO_14;
            break;
        default:
            break;
    }
    return (name);
}

PLUM_PRIVATE
plum_u32 hal_hi_gpio_func(plum_u32 id)
{
    plum_u32 pin = 0;
    switch (PLUM_HAL_GPIO_PIN(id)) {
        case 0:
            pin = HI_IO_FUNC_GPIO_0_GPIO;
            break;
        case 1:
            pin = HI_IO_FUNC_GPIO_1_GPIO;
            break;
        case 2:
            pin = HI_IO_FUNC_GPIO_2_GPIO;
            break;
        case 3:
            pin = HI_IO_FUNC_GPIO_3_GPIO;
            break;
        case 4:
            pin = HI_IO_FUNC_GPIO_4_GPIO;
            break;
        case 5:
            pin = HI_IO_FUNC_GPIO_5_GPIO;
            break;
        case 6:
            pin = HI_IO_FUNC_GPIO_6_GPIO;
            break;
        case 7:
            pin = HI_IO_FUNC_GPIO_7_GPIO;
            break;
        case 8:
            pin = HI_IO_FUNC_GPIO_8_GPIO;
            break;
        case 9:
            pin = HI_IO_FUNC_GPIO_9_GPIO;
            break;
        case 10:
            pin = HI_IO_FUNC_GPIO_10_GPIO;
            break;
        case 11:
            pin = HI_IO_FUNC_GPIO_11_GPIO;
            break;
        case 12:
            pin = HI_IO_FUNC_GPIO_12_GPIO;
            break;
        case 13:
            pin = HI_IO_FUNC_GPIO_13_GPIO;
            break;
        case 14:
            pin = HI_IO_FUNC_GPIO_14_GPIO;
            break;
        default:
            break;
    }
    return (pin);
}

PLUM_PRIVATE
hi_gpio_idx hal_hi_gpio_idx(plum_u32 id)
{
    hi_gpio_idx idx = HI_GPIO_IDX_MAX;

    switch (PLUM_HAL_GPIO_PIN(id)) {
        case 0:
            idx = HI_GPIO_IDX_0;
            break;
        case 1:
            idx = HI_GPIO_IDX_1;
            break;
        case 2:
            idx = HI_GPIO_IDX_2;
            break;
        case 3:
            idx = HI_GPIO_IDX_3;
            break;
        case 4:
            idx = HI_GPIO_IDX_4;
            break;
        case 5:
            idx = HI_GPIO_IDX_5;
            break;
        case 6:
            idx = HI_GPIO_IDX_6;
            break;
        case 7:
            idx = HI_GPIO_IDX_7;
            break;
        case 8:
            idx = HI_GPIO_IDX_8;
            break;
        case 9:
            idx = HI_GPIO_IDX_9;
            break;
        case 10:
            idx = HI_GPIO_IDX_10;
            break;
        case 11:
            idx = HI_GPIO_IDX_11;
            break;
        case 12:
            idx = HI_GPIO_IDX_12;
            break;
        case 13:
            idx = HI_GPIO_IDX_13;
            break;
        case 14:
            idx = HI_GPIO_IDX_14;
            break;
        default:
            break;
    }

    return (idx);
}

PLUM_PRIVATE
plum_s32 hal_hi_gpio_dir(plum_u32 id, plum_hal_gpio_com_cof_t cof)
{
    plum_s32 rc = PLUM_ECODE_OK;

    do {
        hi_io_name io_name = hal_hi_gpio_name(id);
        LOG_D("io name        :%d", io_name);
        plum_u32 func = hal_hi_gpio_func(id);
        LOG_D("io func        :%d", func);
        rc = hi_io_set_func(io_name, func);
        if (rc) {
            LOG_E("hi_io_set_func err,rc:0x%08X", rc);
            rc = PLUM_ECODE_EIO;
            break;
        }

        hi_gpio_idx idx = hal_hi_gpio_idx(id);
        LOG_D("io idx         :%d", idx);
        switch (cof) {
            case PLUM_HAL_GPIO_MODE_ANALOG:
                break;

            case PLUM_HAL_GPIO_MODE_INPUT:
                hi_gpio_set_dir(idx, HI_GPIO_DIR_IN);
                hi_io_set_pull(io_name, HI_IO_PULL_NONE);
                break;
            case PLUM_HAL_GPIO_MODE_INPUT_UP:
                hi_gpio_set_dir(idx, HI_GPIO_DIR_IN);
                hi_io_set_pull(io_name, HI_IO_PULL_UP);
                break;
            case PLUM_HAL_GPIO_MODE_INPUT_DOWN:
                hi_gpio_set_dir(idx, HI_GPIO_DIR_IN);
                hi_io_set_pull(io_name, HI_IO_PULL_DOWN);
                break;
            case PLUM_HAL_GPIO_MODE_OUT_PP:
                hi_gpio_set_dir(idx, HI_GPIO_DIR_OUT);
                hi_io_set_pull(io_name, HI_IO_PULL_NONE);
                break;
            case PLUM_HAL_GPIO_MODE_OUT_OD:
                break;
            case PLUM_HAL_GPIO_MODE_OUT_OD_UP:
                break;
            case PLUM_HAL_GPIO_MODE_OUT_OD_DOWN:
                break;
            case PLUM_HAL_GPIO_MODE_AF_PP:
                break;
            case PLUM_HAL_GPIO_MODE_AF_OD:
                break;
            case PLUM_HAL_GPIO_MODE_AF_INPUT:
                break;
            default:
                break;
        }

    } while (0);

    return (rc);
}

PLUM_PRIVATE
hi_gpio_irq_t *hal_hi_gpio_irq_apply(plum_u32 id, plum_void (*cb)(plum_u32 id))
{
    hi_gpio_irq_t *node = plum_null;

    do {
        node = (hi_gpio_irq_t *)malloc(sizeof(hi_gpio_irq_t));
        if (!node) {
            break;
        }

        memset(node, 0, sizeof(hi_gpio_irq_t));
        node->func = cb;
        node->id   = id;
    } while (0);

    return (node);
}

PLUM_PRIVATE
hi_gpio_irq_t *hal_hi_gpio_irq_find(plum_u32 id)
{
    hi_gpio_irq_t *node = plum_null;

    struct list_head *pos;
    list_for_each(pos, &gpio_irq_head.list)
    {
        node = list_entry(pos, hi_gpio_irq_t, list);
        if (node->id == id) {
            break;
        }
    }

    return (node);
}

PLUM_PRIVATE
plum_s32 hal_hi_gpio_irq_insert(hi_gpio_irq_t *node)
{
    plum_s32 rc = PLUM_ECODE_OK;

    do {
        if (!node) {
            rc = PLUM_ECODE_EPARA;
            break;
        }

        list_add(&node->list, &gpio_irq_head.list);
    } while (0);

    return (rc);
}

PLUM_PRIVATE
plum_s32 hal_hi_gpio_irq_del(hi_gpio_irq_t *node)
{
    plum_s32 rc = PLUM_ECODE_OK;

    do {
        if (!node) {
            rc = PLUM_ECODE_EPARA;
            break;
        }

        list_del(&node->list);
    } while (0);

    return (rc);
}

plum_void hal_hi_gpio_irq_handle(plum_void *arg)
{
    plum_u32 id = *(plum_u32 *)arg;

    hi_gpio_irq_t *node = hal_hi_gpio_irq_find(id);
    if (!node) {
        LOG_E("not find the irq,id:%d", id);
        return;
    }
    else {
        LOG_D("catch gpio irq,id:%d", id);
        node->func(id);
    }
}

PLUM_PRIVATE
plum_s32 hal_hi_gpio_irq(plum_u32 id, plum_hal_gpio_irq_cof_t *cof)
{
    plum_s32 rc = PLUM_ECODE_OK;

    do {
        hi_io_name io_name = hal_hi_gpio_name(id);
        LOG_D("io name    :%d", io_name);
        hi_gpio_idx idx = hal_hi_gpio_idx(id);
        LOG_D("io idx     :%d", idx);
        plum_u32 func = hal_hi_gpio_func(id);
        LOG_D("io func    :%d", func);
        rc = hi_io_set_func(io_name, func);
        if (rc) {
            LOG_E("hi_io_set_func err,rc:0x%08X", rc);
            rc = PLUM_ECODE_EIO;
            break;
        }

        rc = hi_gpio_set_dir(idx, HI_GPIO_DIR_IN);
        if (rc) {
            LOG_E("hi_gpio_set_dir err,rc:0x%08X", rc);
            rc = PLUM_ECODE_EIO;
            break;
        }

        hi_gpio_irq_t *node = hal_hi_gpio_irq_apply(id, cof->irq_handle);
        if (rc) {
            LOG_E("hal_hi_gpio_irq_apply err");
            rc = PLUM_ECODE_EMEM;
            break;
        }

        rc = hal_hi_gpio_irq_insert(node);
        if (rc) {
            LOG_E("hal_hi_gpio_irq_insert err,rc:%d", rc);
            break;
        }

        switch (cof->trip) {
            case PLUM_HAL_GPIO_IRQ_FALLING_EDGE:
                rc = hi_gpio_register_isr_function(
                    idx, HI_INT_TYPE_EDGE, HI_GPIO_EDGE_FALL_LEVEL_LOW,
                    hal_hi_gpio_irq_handle, &node->id);
                LOG_D("set gpio falling irq,id:%d", node->id);
                break;

            case PLUM_HAL_GPIO_IRQ_RISING_EDGE:
                rc = hi_gpio_register_isr_function(
                    idx, HI_INT_TYPE_EDGE, HI_GPIO_EDGE_RISE_LEVEL_HIGH,
                    hal_hi_gpio_irq_handle, &node->id);
                LOG_D("set gpio rising irq,id:%d", node->id);
                break;

            case PLUM_HAL_GPIO_IRQ_BOTH_EDGE:
                // not support
                break;

            case PLUM_HAL_GPIO_IRQ_HIGH_LEVEL:
                rc = hi_gpio_register_isr_function(
                    idx, HI_INT_TYPE_LEVEL, HI_GPIO_EDGE_RISE_LEVEL_HIGH,
                    hal_hi_gpio_irq_handle, &node->id);
                LOG_D("set gpio high level irq,id:%d", node->id);
                break;

            case PLUM_HAL_GPIO_IRQ_LOW_LEVEL:
                rc = hi_gpio_register_isr_function(
                    idx, HI_INT_TYPE_EDGE, HI_GPIO_EDGE_FALL_LEVEL_LOW,
                    hal_hi_gpio_irq_handle, &node->id);
                LOG_D("set gpio low level irq,id:%d", node->id);
                break;

            default:
                break;
        }
        if (rc) {
            LOG_E("hi_gpio_register_isr_function err,rc:0x%08X", rc);
            rc = PLUM_ECODE_EIO;
            hal_hi_gpio_irq_del(node);
            break;
        }
    } while (0);

    return (rc);
}

/*****************************************************************************
 * Public Functions
 ****************************************************************************/

PLUM_PUBLIC
plum_s32 plum_hal_gpio_init(plum_u32 id, plum_hal_gpio_cof_t *cof)
{
    plum_s32 rc = PLUM_ECODE_OK;

    do {
        if (!PLUM_HAL_ID_IS_GPIO(id)) {
            rc = PLUM_ECODE_EPARA;
            break;
        }

        if (!gpio_irq_head.list.next) {
            INIT_LIST_HEAD(&gpio_irq_head.list);
            hi_gpio_init();
        }

        if (cof->mode == PLUM_HAL_GPIO_MODE_COMMON) {
            rc = hal_hi_gpio_dir(id, cof->config.com);
        }
        else if (cof->mode == PLUM_HAL_GPIO_MODE_IRQ) {
            rc = hal_hi_gpio_irq(id, &cof->config.irq);
        }

    } while (0);

    return (rc);
}

PLUM_PUBLIC
plum_bit plum_hal_gpio_read(plum_u32 id)
{
    plum_bit sta;

    hi_gpio_idx idx = hal_hi_gpio_idx(id);
    hi_gpio_dir dir;
    hi_gpio_get_dir(idx, &dir);

    if (dir == HI_GPIO_DIR_IN) {
        hi_gpio_get_input_val(idx, (hi_gpio_value *)&sta);
    }
    else if (dir == HI_GPIO_DIR_OUT) {
        hi_gpio_get_output_val(idx, (hi_gpio_value *)&sta);
    }

    return (sta);
}

PLUM_PUBLIC
plum_s32 plum_hal_gpio_write(plum_u32 id, plum_hal_gpio_sta_t sta)
{
    plum_s32 rc = PLUM_ECODE_OK;

    hi_gpio_idx idx = hal_hi_gpio_idx(id);

    switch (sta) {
        case PLUM_HAL_GPIO_LOW:
        case PLUM_HAL_GPIO_HIGH:
            rc = hi_gpio_set_output_val(idx, (hi_gpio_value)sta);
            if (rc) {
                rc = PLUM_ECODE_EIO;
            }
            break;
        case PLUM_HAL_GPIO_TOG:
        {
            hi_gpio_value value;
            hi_gpio_get_output_val(idx, &value);

            rc = hi_gpio_set_ouput_val(idx, !value);
            if (rc) {
                rc = PLUM_ECODE_EIO;
            }
        } break;
        default:
            break;
    }

    return (rc);
}

PLUM_PUBLIC
plum_void plum_hal_gpio_irq_enable(plum_u32 id)
{
    hi_gpio_irq_t *node = hal_hi_gpio_irq_find(id);
    if (!node) {
        LOG_E("the id not registered a irq,id:%d", id);
        return;
    }

    hi_irq_enable(GPIO_IRQ);
}

PLUM_PUBLIC
plum_void plum_hal_gpio_irq_disable(plum_u32 id)
{
    hi_gpio_irq_t *node = hal_hi_gpio_irq_find(id);
    if (!node) {
        LOG_E("the id not registered a irq,id:%d", id);
        return;
    }

    hi_irq_disable(GPIO_IRQ);
}

/****************************************************************************/
/*                                                                          */
/*  End of file.                                                            */
/*                                                                          */
/****************************************************************************/
